The present invention generally relates to a semiconductor integrated circuit and more particularly relates to a semiconductor integrated circuit realizing an electrical interface.
An average rate at which data is transferred between electronic units has been rising day after day to catch up with recent remarkable development of multimedia electronic equipment. The IEEE 1394, which is an international standard for a high performance serial bus, has attracted much attention as a strong candidate for coping with such high-speed applications.
In compliance with the IEEE 1394, two discrete electronic units are coupled together by way of two twisted pair signal lines (which will be herein called a xe2x80x9ctwisted-pair cablexe2x80x9d collectively). In this cable, each twisted pair is driven by a differential signal with a small amplitude of about 200 mV. Each of the electronic units that should be coupled together via the twisted-pair cable includes an LSI realizing an electrical interface (or physical channel interface) for the IEEE 1394 physical layer. So an LSI of this type will be herein called a xe2x80x9cPHY chipxe2x80x9d. The PHY chip includes cludes a circuit for driving the twisted pairs and a circuit for receiving differential signals transmitted through the twisted pairs. Examples of the differential signal receivers include a data receiver and an arbitration comparator. The differential signals, transmitted through the twisted pairs, have a small amplitude, and are amplified by a receiver of any of those types.
Also, according to the IEEE 1394, the in-phase potential of each differential signal on the twisted-pair cable is sometimes controlled in such a manner as to represent some information. This potential control is carried out for a speed signaling or self identification process. In a speed signaling process, for example, a current is shunted from a twisted pair into the ground at one of the units coupled together. As a result, the in-phase potential of the differential signal on the twisted pair drops. Then, the in-phase potential variation is sensed at the other unit. And the transfer rate is determined in accordance with the variation sensed. The IEEE 1394 provides transfer rates at multiple levels, and a transfer rate at the most appropriate level is selected through the speed signaling process.
The receiver included in the PHY chip is normally implemented as operational amplifiers. Accordingly, if the inphase potential of the differential signal changes steeply, then the output of the receiver may have its logical level inverted verted erroneously even though the logic represented by the differential signal remains the same. In that case, the digital section that receives the output of the receiver may also operate erroneously, thus preventing the system from carrying out its transfer operation as intended. An unwanted phenomenon like this often occurs at an arbitration comparator for which an offset has been set.
It is therefore an object of the present invention to provide a semiconductor integrated circuit that can eliminate the adverse effects possibly caused if its receiver has operated erroneously due to the variation in the in-phase potential of a differential signal.
A semiconductor integrated circuit according to an aspect of the present invention is adapted to realize an electrical interface. The integrated circuit includes receiver, potential sensor and output fixing means. The receiver receives a differential signal that has been transmitted through a twisted pair of signal lines, and outputs a signal in accordance with the differential signal. The potential sensor senses a variation in in-phase potential of the differential signal transmitted through the twisted pair. And the output fixing means fixes an output of the receiver at a certain value if the variation sensed by the potential sensor is equal to or greater than a predetermined level.
In the inventive semiconductor integrated circuit, once a variation in the in-phase potential of a differential signal exceeds a predetermined level, the output of the receiver is fixed at a certain value. Accordingly, even if the receiver operates erroneously due to the in-phase potential variation, the erroneous output of the receiver is not delivered to the next stage (e.g., digital section) that should receive the output of the receiver.
In one embodiment of the present invention, the integrated circuit preferably realizes an electrical interface for the IEEE 1394 physical layer.
In another embodiment of the present invention, the receiver preferably includes an arbitration comparator that receives the differential signal transmitted through the twisted pair and senses three states represented by the differential signal.
In still another embodiment, the potential sensor preferably includes a comparator for comparing the in-phase potential of the differential signal transmitted through the twisted pair to a reference potential.
In yet another embodiment, the certain value is preferably the output of the receiver and associated with a point in time just before the variation sensed by the potential sensor reaches the predetermined level.
In yet another embodiment, the inventive integrated circuit preferably further includes a delay circuit for delaying the output of the receiver.
The integrated circuit according to this embodiment can adjust a time lag between the potential sensor""s sensing the in-phase potential variation of the differential signal and the receiver""s delivery of its output signal to the digital section. Accordingly, it is possible to avoid an unwanted situation where the erroneous output of the receiver happens to reach the digital section before the potential sensor senses the in-phase potential variation.
In yet another embodiment, on receiving the output of the receiver, the fixing means preferably passes the output of the receiver as it is if the variation sensed by the potential sensor is smaller than the predetermined level. Alternatively, if the variation sensed by the potential sensor is equal to or greater than the predetermined level, the fixing means preferably outputs the certain value.
In this particular embodiment, the fixing means preferably includes a latch circuit. If the variation sensed by the potential sensor is equal to or greater than the predetermined level, the latch circuit preferably holds an output value of the receiver. The output value held is associated with a point in time just before the variation sensed by the potential sensor reaches the predetermined level.
A semiconductor integrated circuit according to another aspect of the present invention is also adapted to realize an electrical interface. The integrated circuit includes receiver, driver and output fixing means. The receiver receives a differential signal that has been transmitted through a twisted pair of signal lines, and outputs a signal in accordance with the differential signal. The driver shunts a current with a predetermined value from the twisted pair into the ground for a prescribed period of time. And the output fixing means fixes an output of the receiver at a certain value during the prescribed period.
When a current is shunted from a twisted pair into the ground, a differential signal, transmitted through the twisted pair, has its in-phase potential dropped. In that case, the receiver might operate erroneously due to the in-phase potential variation. In the inventive integrated circuit, however, the output of the receiver is fixed at a certain value during the period in which a current is shunted from the twisted pair into the ground. Accordingly, even if the receiver operates erroneously due to the in-phase potential variation, the erroneous output of the receiver is not delivered to the next stage (e.g., digital section) that should receive the output of the receiver.
In one embodiment of the present invention, the integrated circuit preferably realizes an electrical interface for the IEEE 1394 physical layer.
In another embodiment of the present invention, the receiver preferably includes an arbitration comparator that receives the differential signal transmitted through the twisted pair and senses three states represented by the differential signal.
In still another embodiment, the certain value is preferably the output of the receiver and associated with a point in time just before the prescribed period begins.
In yet another embodiment, the inventive integrated circuit preferably further includes a delay circuit for delaying the output of the receiver.
In yet another embodiment, on receiving the output of the receiver, the fixing means preferably always delivers the output of the receiver except the prescribed period, during which the fixing means outputs the certain value.
In yet another embodiment, the fixing means preferably includes a latch circuit. During the prescribed period, the latch circuit holds an output value of the receiver. The output value held is associated with a point in time just before the prescribed period begins.